Inside the Groq 3 LPU
NVIDIA LP30 Accelerator: Groq 3 LPU Architecture Explained
LP30 is the chip-level building block inside NVIDIA Groq 3 LPX. NVIDIA's public product page calls the device the Groq 3 LPU, while the technical deep dive uses LP30 when describing the chips on each compute tray. A single accelerator is not the normal deployment target; 256 LP30 chips are coordinated inside an LPX rack.
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LP30 Chip, Tray and Rack Calculator
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Quick answer
LP30 is the LPU chip, LPX is the rack-scale system
Each Groq 3 LP30 LPU provides 500 MB SRAM, 150 TB/s SRAM bandwidth and 2.5 TB/s scale-up bandwidth. Eight LP30 chips form an LPX compute tray, and 256 chips form the rack-scale inference engine. The architecture is compiler scheduled to keep computation and communication deterministic.
Do not shop for LP30 like a PCIe inference card
The useful planning unit is the qualified LPX system. Chip and tray specifications explain the architecture, but a buyer should not assume an LP30 can be installed in an arbitrary server. Use per-chip arithmetic to understand scaling and use OEM rack documentation for deployment.
LP30 accelerator specifications and scaling
Chip-level values are most useful when related back to the eight-chip tray and 256-chip LPX rack.
| Metric | One LP30 LPU | Eight-chip compute tray | 256-chip LPX rack |
|---|---|---|---|
| Processor count | 1 | 8 | 256 |
| SRAM | 500 MB | 4 GB | 128 GB |
| SRAM bandwidth | 150 TB/s | 1.2 PB/s | 40 PB/s published aggregate |
| Scale-up bandwidth | 2.5 TB/s | 20 TB/s | 640 TB/s |
| FP8 compute | Not separately published in the cited table | 9.6 PFLOPS | 315 PFLOPS |
| Role | Language processing unit | Modular compute building block | Deployable rack-scale inference engine |
Before you use the result for procurement
Benchmark the exact workload
Keep the model, context length, output length, concurrency, precision and serving-software version beside every TPS result.
Separate context from generation
LPX is positioned around low-latency token generation; Rubin and Rubin CPX handle different context-heavy work. Measure both phases.
Treat rack specs as architecture
LPUs, SRAM and internal bandwidth explain the system design but do not by themselves predict application throughput.
Verify the current OEM design
Use qualified system documentation for rack power, cooling, networking, serviceability and supported configuration before procurement.
LP30 is the chip name used inside the Groq 3 LPX architecture
NVIDIA consumer-facing material primarily says Groq 3 LPU, while the technical blog describes 256 Groq 3 LP30 chips and eight LP30 chips per compute tray. Both references point to the same processor family inside the LPX system. Using the full phrase “Groq 3 LP30 LPU” avoids treating LP30 as a separate retail accelerator line.
The distinction also improves search accuracy. An LPX rack is a complete inference system; LP30 describes the underlying processing chip. Cloudzat keeps both names on this page so engineers looking for either term can map the architecture correctly.
One LP30 carries 500 MB of on-chip SRAM
The LPU uses SRAM as a core part of its low-latency execution model. NVIDIA publishes 500 MB per chip. On-chip SRAM has much lower access latency than large external memory, allowing the processor to keep frequently used data close to the compute units and to make memory timing more predictable.
The tradeoff is capacity. Five hundred megabytes is not enough to hold a modern large language model by itself, so the architecture distributes work across many chips and uses additional memory tiers. That is why the chip should be understood as part of the rack rather than evaluated as a self-contained model host.
The published SRAM bandwidth is 150 TB/s per chip
NVIDIA lists 150 TB/s of SRAM bandwidth for each Groq 3 LPU. That very high local-memory bandwidth supports the deterministic schedule by reducing the time compute units wait for data that has already been placed in SRAM. Across an eight-chip tray, the published aggregate is 1.2 PB/s.
Bandwidth arithmetic explains architecture but does not predict tokens per second. A model can be limited by communication, compute, context processing or other memory tiers. Benchmark the complete serving path instead of dividing a bandwidth figure by model size.
Each LP30 also participates in a high-bandwidth chip-to-chip network
The LPU provides 2.5 TB/s of scale-up bandwidth according to NVIDIA. The long-context technical description says each chip has 96 chip-to-chip links running at 112 Gbps. The compiler sees those communication resources and can plan when data moves between processors.
This direct network is fundamental because a large model is distributed. The system has to coordinate many chips without allowing communication jitter to dominate output-token latency. LP30 is therefore as much a networked processor design as a standalone compute block.
Eight LP30 chips form one compute tray
The LPX technical deep dive lists eight chips per tray, producing 4 GB of SRAM, 1.2 PB/s SRAM bandwidth, 20 TB/s scale-up bandwidth and 9.6 PFLOPS of FP8 inference compute at the tray level. Additional DRAM paths are also described through fabric expansion logic and the host CPU.
A tray gives hardware teams a useful modular boundary for service and architecture discussions. It still is not the normal independent application target. Production scheduling is designed around the connected LPX rack and its relationship with Vera Rubin NVL72.
A rack scales the design to 256 processors
Thirty-two groups of eight chips equal 256 LP30 accelerators, matching NVIDIA's rack processor count. The published rack resources include 128 GB aggregate SRAM, 40 PB/s SRAM bandwidth and 640 TB/s scale-up bandwidth. NVIDIA also lists 12 TB DDR5 and 315 PFLOPS FP8 at rack scale.
Those totals show why the system is marketed as a rack-scale accelerator rather than a card. The software can treat a large pool of tightly coordinated processors as one inference engine for supported workloads.
Deterministic execution starts in the compiler
A traditional processor often makes many scheduling and arbitration decisions at runtime. The Groq approach pushes more of that planning into the compiler. NVIDIA says the compiler can know compute-unit availability, memory placement and communication timing before the workload begins, generating a detailed execution schedule.
This model is attractive for latency-sensitive inference because uncertainty can translate into jitter. The advantage is most meaningful when the model maps well to the compiler and serving system. Unsupported or rapidly changing workloads may value general-purpose GPU flexibility more.
Communication and computation can be overlapped intentionally
Because the execution plan includes chip-to-chip transfers, the compiler can schedule communication while other compute proceeds. This overlap is a key mechanism for scaling tensor-parallel work without letting data movement dominate every step. The long-context technical blog highlights that behavior as important at small batch sizes.
Application architects should still distinguish internal overlap from external service latency. A tool call across the internet, slow retrieval database or congested scale-out fabric can add far more delay than the accelerator schedule. End-to-end profiling remains necessary.
LP30 is optimized for inference rather than a broad accelerator portfolio
The LPU is purpose-built around language-model serving and predictable token generation. It does not carry the same general CUDA programming model or mixed-workload positioning as a Rubin GPU. That specialization is the source of both its appeal and its limitations.
Buyers should map production requirements to supported software before assuming the chip can absorb arbitrary AI jobs. The strongest case appears when the workload is stable, high-volume and sensitive to generation latency.
Per-chip peak values should not be used to invent a retail comparison
It would be misleading to compare one LP30 with one gaming or data-center GPU by multiplying or dividing isolated peak figures. LP30 is deployed as part of a 256-chip rack, while GPUs have different memory systems, interconnects and workload roles. There is no universal conversion such as “one LP30 equals X GPUs.”
Use the LPX-versus-GPU page in this cluster for a functional comparison and run model-specific benchmarks when evaluating economics. The chip calculator above exists to explain scaling, not to create an equivalence ratio.
Support infrastructure is sourced separately from the accelerator chips
An LPX rack still connects to storage, external network and facility power systems. Those components have conventional product markets and can be monitored for price trends, which is why Cloudzat surfaces relevant NIC, NVMe and metered-PDU listings.
The marketplace rows do not imply those products are validated for a particular LPX OEM implementation. Exact interfaces, firmware, optics and rack power equipment must be checked against the system vendor. The LP30 chips themselves are not presented as Amazon products.
Treat chip specifications as living platform documentation
LPX moved into full production in August 2026 and the software and platform ecosystem will continue evolving. NVIDIA can update product specifications, model support or system configurations. An engineering document should therefore include the official source and date rather than copying a static table without provenance.
Cloudzat keeps the source links visible and avoids inventing unknown per-chip values. If current NVIDIA documentation conflicts with this page, use the manufacturer's latest data and the signed OEM configuration for procurement.
Methodology and sources
LP30 terminology and values are taken from NVIDIA's Groq 3 LPX technical documentation. Arithmetic in the tool simply scales user-entered per-chip and per-tray values; it does not claim linear application performance.
- NVIDIA Groq 3 LPX product page
- NVIDIA technical blog: inside Groq 3 LPX
- NVIDIA technical blog: LPX long-context interactivity
- NVIDIA Groq 3 LPX full-production announcement
- NVIDIA technical blog: Vera Rubin POD architecture
- NVIDIA Vera Rubin NVL72
As an Amazon Associate, Cloudzat may earn from qualifying purchases. Marketplace listings on these pages cover adjacent networking, storage, memory or power hardware only. They are not represented as LP30 chips, LPX trays or qualified Vera Rubin rack components. Verify exact models, warranty, interfaces and current OEM documentation before purchase.
Frequently asked questions
What is NVIDIA LP30?
LP30 is the chip designation used for the Groq 3 LPU inside the NVIDIA Groq 3 LPX rack-scale inference system.
Is LP30 the same as LPX?
No. LP30 is the LPU chip; LPX is the rack-scale system built from 256 of those accelerators.
How much SRAM does LP30 have?
NVIDIA lists 500 MB per Groq 3 LPU.
What is LP30 SRAM bandwidth?
150 TB/s per chip.
What is LP30 scale-up bandwidth?
2.5 TB/s per chip.
How many LP30 chips are on a compute tray?
Eight.
How many LP30 chips are in a rack?
256.
Can I install an LP30 in a normal PCIe server?
Cloudzat does not treat LP30 as a retail PCIe card. It is part of the qualified LPX rack architecture.
Does LP30 run CUDA?
The LPU uses a different compiler-scheduled architecture. CUDA is associated with NVIDIA GPUs such as Rubin and Rubin CPX.
What should I benchmark on LP30/LPX?
Benchmark the full LPX-backed service using your exact model, context, output length, concurrency and software version rather than trying to predict TPS from chip specs.